Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FINFET is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FINFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FINFET the transistor channel is formed along the vertical sidewalls of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
FINFET ICs have traditionally been fabricated using semiconductor on insulator (SOI) substrates. There are significant advantages, however, to fabricating FINFET ICs on a bulk semiconductor substrate, including the significantly lower cost and higher crystalline quality of a bulk semiconductor substrate compared to a SOI substrate. Some problems that are easily solved when using SOI substrates must be addressed when fabricating FINFET ICs on a bulk semiconductor substrate. When using a SOI substrate, isolation between fins is achieved by etching away all of the semiconductor material between the fins, leaving the fins extending upwardly from the underlying insulating material. In addition, with an SOI substrate all current flow between source and drain regions is controlled by the gate electrode because there is no parasitic conduction path through an underlying semiconductor substrate. The issue of isolation between fins in a FINFET IC fabricated on a bulk semiconductor substrate is addressed in Patent Application Publication US2010/0015778, assigned to Advanced Micro Devices, Inc. That Application does not address, however, the parasitic conduction path that exists between source and drain through the underlying semiconductor substrate and under the gate controlled channel in a conventional FINFET fabricated on a bulk semiconductor substrate.
Accordingly, it is desirable to provide a bulk FINFET IC that overcomes the problem of parasitic conduction between transistor source and drain. In addition, it is desirable to provide methods for fabricating a FINFET IC on a bulk semiconductor substrate that eliminate parasitic conduction paths between transistor source and drain regions. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.